Startup Vayavya unveils automated device driver generator
BENGALURU, India — Vayavya Labs is launching an automated device driver generator framework that the company claims will bring discipline through its formal language-based approach.
Device driver generation is error prone and hard to maintain since there is no standard process across diverse platforms. Vayavya said its DDGen generator framework addresses these problems while reducing development time and coding effort.
The beta version, now undergoing testing with two semiconductor manufacturers, supports PCI drivers and will eventually support USB and Ethernet. It currently supports Linux and TI BIOS operating systems.
"Device generation by tools has mainly been a research topic. Those who attempted it did so purely from a hardware (device) aspect or from a software point of view," said R.K. Patil, CEO and co-founder of Vayavya (Belgaum, India). Patil said some researchers focused on "how to capture the register and its programming part, and then went on generate various device access methods. But for some reason, no attempt to capture the software needs while generating the device access methods was made."
DDGen captures device specifications and programming models using a formal language approach, then extends the concept to capture the run-time environment specification. "The real benefit comes when we look at both these specifications and then use the tool to generate the code. The tools model an expert system [acting] on two inputs, makes certain decisions based on commonly observed patterns (code structures used in manually written drivers) and then outputs the driver code," Patil said.
Chief analyst Daya Nadamuni of Gary Smith EDA said "a proprietary language may be a stumbling block for rapid adoption because it involves a learning curve. If it is targeting primarily embedded software engineers, they are familiar with ANSI C. But if it is targeting SoC designers, they are more attuned to System C. Adoption rates may vary based on the familiarity with the approach and the language."
Nadamuni cited concerns about other products based on proprietary languages. Vayavya "may need to be System C compliant as well and I do not see any System C compliance" in DDGen, Nadamuni said. DDGen could be made compliant with System C as the tool matures, Patil said, adding that he sees a movement towards SystemVerilog and Spriit specifications which address the ESL market.
"The tool proposes formalization of certain activities in current SoC/ASIC and software development flows and the time needed to incorporate changes in design flows. We will adopt Spirit 1.2 specifications with extensions and enhancements, which should address some concerns arising from the proprietary language," he said.
The beta version DDGen is for driver generation only, but also targets embedded software engineers. Current SoC design cycles are software intensive, mainly for device functional verification. Board support packages and programming model definitions are generally carried out by hardware designers.